A Parallel Test Generation for Combinational Circuits Based on Boolean Satisfiability - ASIC Conference and Exhibit, 1996. Proceedings., Ninth Annual IEEE International

This paper presents an efficient parallel algebraic algorithm to implement ATPG for combinational circuits using the Boolean satisfiability on a distributed Computing environment. Path-Oriented Expanded Implication Graph(POE1G) of a combinational circuit is taken as a heuristics guide to improve the traditional stochastic calculation of Boolean satisfiability formula of a circuit. We propose a efficient method to establish the simple reduction form complexed ternary clauses to binary ones in a circuit. Based on the POEIG, a circuit is partitioned into cones according to fanout-reconvergent pairs in the circuit. To improve the performance of traditional parallel algorithms, we conduce two different parallel strategies: the first for a local cone generated by our segmentation scheme, the second for a global circuit, according to the POEIG of a circuit. We introduce two important concepts for implementing our ATPG, correlative subset for a cone and precedent critical path rule within a cone in a circuit so that we can sensitize any common subpaths or cones only once. We parallel process the subcomputings of different cones based on the parallel essence of POEIG based on a decomposition algorithm[Li and Kameda941.